1. Technical Field
The present invention relates generally to processors and computing systems, and more particularly, to a simultaneous multi-threaded (SMT) processor.
2. Description of the Related Art
Present-day high-speed processors include the capability of simultaneous execution of instructions, speculative execution and loading of instructions and simultaneous operation of various resources within a processor. In particular, it has been found desirable to manage execution of one or more threads within a processor, so that more than one execution thread may use the processor without generating conflicts between threads and while using processor resources more effectively than they are typically used by a single thread.
Prior processor designs have dealt with the problem of managing multiple thread via a hardware state switch from execution of one thread to execution of another thread. Such processors are known as hardware multi-threaded (HMT) processors, and as such, can provide a hardware switch between execution of one or the other thread. An HMT processor overcomes the limitations of waiting on an idle thread by permitting the hardware to switch execution to a non-idle thread. Execution of both threads can be performed not simultaneously, but by allocating execution slices to each thread when neither are idle. However, the execution management and resource switching (e.g., register swap out) in an HMT processor introduce overhead that makes the processor less efficient that a single-threaded scheme.
Additionally, resources such as queues for instructions and data, tables containing rename mapping and tag values that enable instruction execution are duplicated in an HMT processor in order to provide for switching execution between threads. While a first thread is running, a second thread's resources are typically static values that are retained while the second thread is not running so that execution of the second thread can be resumed.
However, in a simultaneous multi-threaded (SMT) processor, two or more threads may be simultaneously executing within a single processor core. In an SMT processor, the threads may each use processor resources not used by another thread, and thus true simultaneous use of the processor requires effective management of processor resources among executing threads.
Rename registers are so-called because they implement virtual registers that are actually associations between physical storage registers and one or more logical register “names” or “maps”. A logical unit known as a mapper associates one or more virtual registers with a physical storage register. Further, sets of “architected” registers within rename register resources are generally allocated on a fixed basis to each thread. Reallocation of fixed entries presents a particular problem, as during execution of instruction streams for one or more threads, the mapper may fill up or fragment with maps for one or more threads, so a physical division of mapper entries within the rename resources is impractical and a logical division would require extensive internal logic or an external housekeeping unit.
In an HMT processor, the mapper and physical storage would typically be duplicated. In an SMT processor, it is desirable to allocate fixed resources within rename registers between a number of threads executing in the SMT processor.
It is therefore desirable to provide an SMT processor and rename register reallocation methodology that can effectively manage processor resources when one or more threads are executing within the processor.